Cadence Electronics (NASDAQ: CDNS) recently announced the launch of a new application that significantly enhances its flagship product Palladium? The functions of the Z2 Enterprise Simulation System. These domain specific applications can help customers manage the increasing complexity of system design, improve system level accuracy, and accelerate low-power verification, especially suitable for some advanced chip fields such as artificial intelligence and machine learning (AI/ML), ultra large scale, and mobile communication.

Today's designs are becoming increasingly complex, and customers require top-notch capacity, performance, and debugging efficiency to meet product time to market requirements. The newly launched Cadence? Applications and updates provide industry-leading performance and functionality, helping to easily address these growing challenges. The newly added enhanced Palladium applications include:

·Four state hardware simulation application: The industry's first four state hardware simulation function can accelerate simulation tasks that require X-state propagation, such as low-power verification of complex SoCs with multiple switching power supply domains.

·Real number modeling application: The industry's first real number model hardware simulation function, which can accelerate the simulation of mixed signal design.

·Dynamic Power Analysis Application: A new generation of large-scale parallel architecture that can perform power analysis on complex SoCs for billions of logic gates and millions of clock cycles, with a speed five times faster than previous versions.

"In order to keep up with today's advanced SoC design requirements, customers need a high-performance hardware simulation solution that also has fast and predictable compilation capabilities as well as powerful debugging capabilities," said Dhiraj Goswami, Vice President of Hardware System Validation Research and Development at Cadence, "With the launch of these new Palladium applications, customers can accelerate their X-state propagation and hardware simulation of mixed signals, which is still the first in the industry."

The Palladium Z2 hardware simulation system is part of the broader Cadence Verification Suite validation suite, supporting the company's Intelligent System Design? Strategy aimed at achieving excellent SoC design. For more information about the newly released enhanced Palladium Z2 application, please visit www.cadence.com/go/Palladiumapps.

Customer feedback:

NVIDIA has been utilizing the Cadence Palladium Simulation hardware simulation platform for many years to complete our early software development, hardware and software validation, and debugging tasks. We work closely with Cadence to provide development advice for new Palladium applications, including the industry's first real number modeling and four state hardware simulation applications. With these new applications, we can accelerate and integrate real number modeling structures as our large GPU Part of it is to improve the system level accuracy of analog, digital, and software behaviors, and accelerate product launch

-NVIDIA Corporation

Narendra Konda, Vice President of Hardware Engineering

"MediaTek's innovative SoC covers mobile communication, smart home, and IoT applications. In order to meet customers' growing performance needs, our SoC design has become increasingly complex. Compared to the previous version, Cadence's new generation of dynamic power analysis application for the Palladium Simulation System has helped us increase the power analysis and direct report generation speed of advanced SoC designs by five times."

-MediaTek

Deputy Director Debra Lin

"Samsung needs to leverage top-notch hardware simulation technology to develop the most advanced and complex SoCs. For many years, we have been a loyal user of the Cadence Palladium Simulation System. With the help of new four state hardware simulation applications, we can accelerate low-power verification of complex SoC designs, improve verification accuracy and low-power coverage, and increase overall verification throughput."

-Samsung Electronics

Vice President Seonil Brian Choi

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